Verilog digital system design : RT level synthesis, testbench, and verification / Zainalabedin Navabi.
Material type:
- 0071445641
- 9780071445641
Item type | Current library | Home library | Collection | Shelving location | Call number | Status | Date due | Barcode | |
---|---|---|---|---|---|---|---|---|---|
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UMK Kampus Jeli | UMK Kampus Jeli | DEFAULT | Kampus Jeli Reference Level 1 | TK7885.7 .N36 2006 REF (Browse shelf(Opens below)) | Not for loan | 10020740 | ||
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UMK Kampus Kota | UMK Kampus Kota | DEFAULT | Kampus Kota Audio Visual | TK7885.7 .N36 2006 AV (Browse shelf(Opens below)) | Available | 10020740(CD) |
Includes index.
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